1. Field of the Invention
This invention relates to CMOS semiconductor devices and more particularly to improved dosages of dopant therein.
2. Description of Related Art
In a conventional retrograde process, an implant of a single charge of phosphorous P.sup.+31 is employed to improve the PMOS device punchthrough voltage of the semiconductor device. However, that method limits the PMOS channel length to 1.2 .mu.m on the wafer which is disadvantageous because the chips size would be larger.
U.S. Pat. No. 4,710,477 of Chen for "Method for Forming Latch-up Immune, Multiple Retrograde Well High Density CMOS FET" describes a double retrograde density profile at Col. 5, lines lines 26-27. The Chen patent describes a method producing a multiple P-well implant to improve latch-up, but it is not useful for the purpose of PMOS device gate length reduction.
U.S. Pat. No. 4,761,384 of Neppl et al "Forming Retrograde Twin Wells by Outdiffusion of Impurity Ions in Epitaxial Layer Followed by CMOS Device Processing" shows a method for forming retrograde twin wells. The Neppl et al patent describes a method requiring use of a P-well and N-well implant to produce a retrograde twin well for the purpose of reducing the N+ inside the P-well rule and to reduce the P+ inside the N-well rule. However, with this design the PMOS device gate length is reduced, which is not very useful. Another disadvantage of the Neppl design is that an epitaxial wafer is required for this design is expensive, adding significantly to manufacturing cost.